I2S FIFO configuration register
| RX_DATA_NUM | I2S_RX_TAKE_DATA_INT is triggered when the left and right channel data number in RX FIFO is larger than the value of I2S_RX_DATA_NUM[5:0]. (RX FIFO is almost full threshold.) |
| TX_DATA_NUM | I2S_TX_PUT_DATA_INT is triggered when the left and right channel data number in TX FIFO is smaller than the value of I2S_TX_DATA_NUM[5:0]. (TX FIFO is almost empty threshold.) |
| DSCR_EN | Set this bit to enable I2S DMA mode. |
| TX_FIFO_MOD | Transmitter FIFO mode configuration bits |
| RX_FIFO_MOD | Receiver FIFO mode configuration bits |
| TX_FIFO_MOD_FORCE_EN | The bit should always be set to 1 |
| RX_FIFO_MOD_FORCE_EN | The bit should always be set to 1 |
| RX_FIFO_SYNC | force write back rx data to memory |
| RX_24MSB_EN | Only useful in rx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo |
| TX_24MSB_EN | Only useful in tx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo |